Methods and apparatus for emitter detection

ABSTRACT

A method is provided for coordinating detection of emitted signals by a receiver with transmission of signals by a transmitter, wherein the receiver and the transmitter are located on the same platform. The receiver scans a surrounding environment to detect emitted signals in multiple frequency ranges while the transmitter transmits signals in a predetermined frequency range. The receiver may employ dwells which may be defined as receiver configurations. A dwell, when executed, may be used to detect signals in a certain frequency range. If a frequency range of the dwell conflicts with the frequency range of transmitter signals, which may result in interference of transmitter signals with detection of emitted signals, execution of the dwell may be delayed. If the frequency range of the dwell is such that transmitter signals do not interfere with execution of the dwell, the dwell can be executed.

GOVERNMENT SUPPORT

This invention was made with government support under contract numberN00019-05-C-0076 awarded by the Department of the Navy. The governmentmay have certain rights in the invention.

FIELD OF INVENTION

The present invention relates to using a receiver to detecting emittedsignals.

DISCUSSION OF RELATED ART

Electronic Support Measure (ESM) receivers are receivers used to detect,identify, and/or locate emitted electromagnetic signals. Such signalsmay have vastly different signal characteristics (e.g., pulse width andpulse repetition interval) and may be transmitted by a variety ofemitters that transmit in different portions of the frequency spectrum.

Thus, it may be desired to use an ESM receiver to detect signals acrossa wide range of frequencies. This may be accomplished using a set ofdwells which define a duration of scanning within a certain frequencyrange. A dwell may have an associated revisit time that defines howoften the dwell is executed and may also have defined a duration.

SUMMARY OF INVENTION

One embodiment is directed to a method for coordinating detection ofemitted signals with transmission of signals in a device having at leastone transmitter that transmits signals in a first frequency range and atleast one receiver system adapted to execute a plurality of dwells. Themethod comprises acts of: determining a first time at which at least onesignal in the first frequency range is scheduled for transmission by theat least one transmitter; selecting a first dwell from the plurality ofdwells to be executed at the first time; determining whether a frequencyrange of the first dwell conflicts with the first frequency range; andwhen it is determined that the frequency range of the first dwellconflicts with the first frequency range, delaying execution of thefirst dwell. Another embodiment is directed to at least one computerreadable medium, encoded with instructions, that when executed, performthe above-described method.

A further embodiment is directed to at least one receiver system adaptedto execute a plurality of dwells and configurable to operate with atleast one transmitter that transmits signals in a first frequency range.The receiver system comprising: at least one controller that: determinesa first time at which at least one signal in the first frequency rangeis scheduled for transmission by the at least one transmitter; selects afirst dwell from the plurality of dwells to be executed at the firsttime; determines whether a frequency range of the first dwell conflictswith the first frequency range; and when it is determined that thefrequency range of the first dwell conflicts with the first frequencyrange, delays execution of the first dwell.

BRIEF DESCRIPTION OF DRAWINGS

In the drawings:

FIG. 1 is a block diagram illustrating a platform including atransmitter and a receiver, on which some embodiments of the inventionmay be implemented;

FIG. 2A is a block diagram of an ESM receiver that receives an advancedslot notification signal from a data link, in accordance with someembodiments of the invention;

FIG. 2B is a block diagram of an illustrative system, on which someembodiments of the invention may be implemented;

FIGS. 3A and 3B are flowcharts illustrating a process of harmonizing anexecution of receiver dwells with a data link transmission, inaccordance with some embodiments;

FIG. 4 is a schematic diagram illustrating an example of data linktransmission frequency ranges and receiver dwell frequency ranges, inaccordance with some embodiments;

FIG. 5 is a flowchart illustrating a process of determining whetherexecution of a dwell may interfere with a data link transmission, inaccordance with some embodiments; and

FIG. 6 is an illustrative logic diagram illustrating for determining ascheduled transmit-line of a transmitter, in accordance with someembodiments.

DETAILED DESCRIPTION

In some embodiments, a platform that includes an ESM receiver may alsoinclude a transmitter. Thus, the platform may simultaneously transmitsignals via a data link and detect signals emitted by various emitters.Applicants have appreciated that, in some situations, signalstransmitted by the transmitter may interfere with detection of signalsby the receiver.

FIG. 1 is a diagram of an illustrative platform 100 in which someembodiments may be implemented. Platform 100 includes a receiver 102which is any suitable type of receiver, such as, for example, an ESMreceiver. Platform 100 may also include a transmitter 104, which may beused by platform 100 for any suitable purpose, such as, for example, toexchange tactical information with other platforms and/or otherentities. The transmitter 104 may use a data link 106 to transmitsignals. Data link 106 may be any suitable type of data link. Forexample, in some embodiments, data link 106 may be a time divisionmultiple access (TDMA) protocol data link. In embodiments in which thedata link is a TDMA data link, operation of data link 106 may be dividedinto a predefined number of slots. That is, in TDMA systems, a pluralityof transmitters transmit in the same frequency range. So thattransmissions from different transmitters do not interfere, eachtransmitter may be allocated time slots in which it is permitted totransmit. Data link 106 may control the time slots in which the on-boardtransmitter may transmit. The platform 100 may be allocated a particularfrequency range and data link 106 may transmit electromagnetic signalswithin this frequency range.

Concurrently with transmitting signals over data link 106, platform 100may scan a surrounding environment using the receiver 102 which maycollect electromagnetic signals (e.g., signals emitted by emitters 108 aand 108 b in FIG. 1). Receiver 102 may scan the environment (e.g., usinga scan strategy or in any other suitable way) to detect signals ofvarious frequency ranges. In some embodiments, to detect signals ofdifferent frequency having different signal characteristics, receiver102 may execute a series of dwells, which is a series of configurationsof the receiver allowing it to tune to different frequencies and detectsignals having different frequency characteristics.

If receiver 102 is tuned to a frequency which is affected by a data linktransmission, the transmission may interfere with the receiver'sdetection of emitter signals, as described in greater detail below. Toresolve this, the receiver may be “blanked” at a frequency band (orrange) concurrent with data link transmission, which means that thereceiver disregards signals detected during the data link transmission.Blanking may be accomplished using any suitable method. This approachworks well if a data link operates at a low duty cycle, e.g., if thedata link transmits signals approximately 1-2% of its operating time.However, in case of high duty cycles (e.g., the data link transmits25-30% of its operating time), blanking the receiver may compromisetimely detection of emitters. Another way to resolve the conflictbetween data link transmission and signal detection is to suppresstransmission by the data link whenever the data link attempts totransmit signals in a frequency band interfering with the frequency towhich the receiver is tuned. The data link is considered suppressed whenit is precluded from transmitting signals, which may be accomplishedusing any suitable method. However, this may lead to a degradation inperformance of the data link because some of the signals, if suppressed,will not reach their intended recipient(s), which may cause undesirableconsequences.

According to yet another approach, execution of dwells by the receiverin a frequency range that is in or near a frequency range of the datalink transmission may be delayed until a gap in the data linktransmission occurs. Therefore, at a given time, either the receiverdetects emitter signals or the data link transmits signals.Consequently, the receiver may idle, potentially for a long time, untila gap in the data link transmission occurs. This may decrease aperformance of the receiver, and may result in failure to timely detectsome of the emitters in the surrounding environment.

Thus, in some embodiments of the invention, when receiver 102 isconfigured to detect signals in a frequency range that overlaps or isnear the frequency at which the data link transmits, detection of thesesignals may be delayed and the receiver may be configured to detectsignals in a non-conflicting frequency range during the data linktransmission. This may be done in any suitable way, as the invention isnot limited in this respect. In some embodiments, an advanced slotnotification (ASN) signal may be provided by data link 106 to receiver102 to notify the receiver in advance that a particular data link isscheduled to transmit at a particular time. In response, receiver 102may determine whether the transmission would interfere with detection,and, if so, may tune to a frequency range not conflicting with thefrequency range of signals transmitted by data link 106.

FIG. 2A is a block diagram illustrating a system 200 wherein data link106 may provide the ASN signal to receiver 102, in accordance with someembodiments. Receiver 102 may include a receiver module 204 comprising aprocessing core of receiver 102 and a controller module 206 controllingreceiver module 204.

In some embodiments of the invention, a system 208 shown in FIG. 2B maybe used. System 208 may be any suitable system, such as, for example, asingle board computer (SBC) (e.g., a SBC located on an airborneplatform, such as, for example, a helicopter or located in any othersuitable location). System 208 may manage detection of emitter signalsand perform signal processing. System 208 may include a fieldprogrammable gate array (FPGA) 210, an operating flight program (OFP)212 and/or any other suitable components. System 208 may be included inor associated with either or both receiver module 204 and controllermodule 206. FPGA 210 may include a logic implementing some embodimentsof the invention, with components implementing of the logic readable andwriteable by SBC 208. OFP 212 may control the operation of FPGA 210. Itshould be appreciated that system 208 and its components are given andtheir operation is discussed hereinbelow by way of example only and notto limit the scope of the invention. It should also be appreciated thatany other suitable devices, systems, programs and applications may beused to implement embodiments of the present invention.

FIGS. 3A and 3B illustrate an example of a process for harmonizingdetection of signals by an ESM receiver and transmission of signals by aTDMA data link, for use in some embodiments of the invention. Theprocess begins at step 300, where a dwell to be executed by the receivermay be “obtained” (e.g., extracted from a sequence buffer). The processcontinues to step 302, where an arbitration process may determinewhether the dwell is an acquisition dwell. An acquisition dwell is adwell which is executed to detect emitted signals. By contrast,non-acquisition dwells are dwells such as time analysis dwells,built-in-test (BIT) dwells, calibration dwells, as well as dwells ofother types. Non-acquisition dwells may be, for example, pulsemodulation analysis (PMA) dwells, scan type discrimination (STD) dwells,and scan modulation analysis (SMA) dwells. Analysis dwells may beexecuted at distinct points at time and may therefore be separated byrigid intervals. Acquisition dwells are not executed at a specified hardtime, but rather may be executed whenever the receiver is available toexecute them.

If, in step 302, it is determined that the current dwell is not anacquisition dwell, the process continues to step 304 where that dwellmay be executed. In embodiments of the invention, executing a dwellmeans configuring receiver 102 to detect emitted signals within acertain frequency range. Non-acquisition dwells either are not disruptedby data link transmission or take precedence over the data linktransmission. Thus, in some embodiments non-acquisition dwells only beexecuted irrespective of the operation of any transmitters.Alternatively, if in step 302 it is determined that the dwell is anacquisition dwell, the process continues to step 306 which may determinewhether a dwell delay queue (or a delay queue) is empty. The delay queueis used to store dwells that detect emitted signals in a frequency rangethat is in conflict with the frequency range of the data linktransmission for later execution. The delay queue may be any suitabledata structure to store information pertaining to dwells that have beendelayed for execution. For each dwell, a time when the dwell was storedin the delay queue may be recorded. In some embodiments, a dwell may bedelayed in the delay queue for a finite predetermined amount of time. Insome embodiments, the delay queue may have a limit on the number ofdwells that may be stored in the delay queue at one time.

If the delay queue is empty, the process continues to step 316 where itis determined whether data link transmission interferes with thescheduled acquisition dwell. The interference, or a conflict, may occurif emitter signals intercepted by the acquisition dwell and the datalink transmission both flow through a common component of a receiver(e.g., receiver 102), such as, for example, an amplifier or a switch,with neither the emitter signals nor the data link transmission beingfiltered out. For example, the data link transmission at a frequencydenoted as Fd may saturate an amplifier, and the emitter signals at afrequency denoted as Fs may pass through the same amplifier, thusgenerating spurious signals at frequencies Fs±Fd, Fs±2Fd, 2Fs±Fd, andother frequencies for all integer multiples. These spurious signals mayoverload the receiver. Furthermore, emitter signal parametermeasurements will be affected by such saturation. For example, emitteramplitude, phase and other parameter measurements may be inaccurate. Insome embodiments, such interference can occur over wide frequencyranges, such as, for example, from 800 MHz and/or greater below the datalink transmission and 1100 MHz and/or greater above the data linktransmission, depending on the receiver design. Thus, for example, oneembodiment in which the data link transmits at 1000 MHz, if a dwell isconfigured to detect emitter signals in a frequency range that differsfrom a frequency range of the data link transmission by 800 MHz-2200MHz, the data link transmission may interfere with the execution of thedwell.

If, at step 316, it is determined that data link transmission interfereswith the scheduled acquisition dwell, the process continues to step 318,where the acquisition dwell may be placed in the delay queue, and theprocess may continue to step 300 where a next dwell may be obtained forexecution. In some embodiments, a dwell may be executed irrespective ofwhether a data link transmission interferes with it, and the data linktransmission may be suppressed. If it is determined, in step 306, thatthe delay queue is not empty, the process continues to step 308 where itmay be determined whether the delay queue is full.

If the delay queue is not full (i.e., a limit on the number of dwellsstored in the delay queue has not been reached), in step 310 it may bedetermined whether a run count is greater than one. The run count of thedelay queue is the number of dwells in the delay queue which, ifexecuted, would not be disrupted by the data link transmission. Forexample, in some embodiments, such dwells may be dwells which are usedto detect signals in frequency ranges that differ from the frequencyrange of the data link transmission by 800 MHz-2200 MHz. If the runcount is greater than one, the process continues to step 312, where adwell may be selected from the delay queue for execution. To select adwell to be executed from the delay queue, any suitable criterion orcriteria may be used. For example, in some embodiments, dwells in thedelay queue may be analyzed in the order that they were enqueued (i.e.,placed in the delay queue) and marked as “must run” or “can run.” Adwell in the delay queue may be marked as “must run” if it has been inthe delay queue for an amount of time that is equal to a predeterminedlimit on the amount of time the dwell can spend in the queue (which maybe a configurable parameter in some embodiments). A “can run” dwell maybe a dwell which has been in the delay queue for an amount of time lessthan the predetermined limit on the amount of time the dwell can spendin the queue and may detect emitted signals within a frequency rangethat does not conflict with a frequency range of the data linktransmission. In some embodiments of the invention, executing a “mustrun” dwell should be prioritized over executing “can run” dwells. If achoice needs to be made among two or more “can run” dwells, a “can run”dwell which has been in the delay queue for the longest amount of timemay be given a priority. It should be appreciated that a dwell to beexecuted may be selected from the delay queue based on any suitablecriteria or in any suitable way, as the invention is not limited in thisrespect.

Once a dwell is selected for execution, the process continues to step304, where the dwell is executed. If at step 310 it is determined thatthe run count is less than or equal to one, which means either thatthere is only one dwell in the delay queue or only one dwell in thedelay queue is suitable for execution, the process continues to step314, where it may be determined whether the run count is equal to one(i.e., whether the data link transmission does not interfere with onedwell in the delay queue, which may indicate that the delay queuecontains one dwell that can or must run). If the run count is equal toone, the process may continue to step 304, where the dwell may beexecuted. If the run count is not equal to one, the process continues tostep 316, where it is determined whether the data link transmissioninterferes with the dwell scheduled for execution. A scheduled dwellwhich has not been placed in the delay queue may be checked to determinewhether its execution may interfere with data link transmission. If thedata link transmission interferes with the dwell, the dwell may bedelayed by placing it in the delay queue. Otherwise, if it is determinedat step 316 that the data link transmission does not interfere with thedwell, the process continues to step 304 where the dwell may beexecuted.

If it is determined, in step 308, that the delay queue is full, theprocess continues to step 320 in FIG. 3B, where an oldest dwell (e.g.,the dwell that has been in the delay queue the longest may be selectedfrom the delay queue. The process then continues to step 322, where itis determined whether the data link transmission interferes with theselected dwell. If the data link transmission does not interfere withthe selected dwell, the process continues to step 324, where theselected dwell may be executed. However, if it is determined that thedata link transmission interferes with the oldest dwell in the delayqueue, the process may continue to step 326, where the data linktransmission may be suppressed and the selected dwell from the delayqueue may then be executed (step 324). Upon executing the selecteddwell, the process continues to step 300.

As discussed above, an acquisition dwell may be executed if the datalink transmission does not interfere with its execution. FIG. 4illustrates the data link transmission, which occurs, in a givenplatform, within a particular frequency range, and acquisition dwells,which may detect signals at different frequency ranges and, at someranges, may interfere with the data link transmission. Thus, blocks 404a-404 d illustrate data link transmit times, while blocks 402 a-402 d,406 a-406 c, and 408 a-408 d illustrate acquisition dwells, of whichacquisition dwells 402 a-402 d may detect emitted signals withinfrequency ranges that are in proximity to a frequency range of transmitslots 404 a-404 d. The data link transmission may therefore interferewith acquisition dwells 402 a-402 d which, in some embodiments, may notbe executed when the data link transmits and may be placed in the delayqueue.

It may be determined whether a data link transmission interferes withdwell execution in any suitable way, as the invention is not limited inthis respect. FIG. 5 is a flowchart illustrating an example of how thisdetermination may be made in some embodiments. The process begins atstep 500 by obtaining a dwell (e.g., a dwell contained in the sequencebuffer or a dwell from the delay queue). The process then continues tostep 502, where an ASN signal is received. The ASN signal indicates thatthe data link is scheduled to transmit at a future time. The processthen continues to step 504, where it is determined if the data linktransmits during execution of the dwell (i.e., whether the current slotis a transmit slot). If the data link transmits during execution of thedwell, the process continues to step 506, where it is determined if afrequency range of the data link transmission interferes with thefrequency range of the dwell. If there is no interference, the processcontinues to step 510, where the dwell is executed. If it is determinedin step 506 that the data link transmission interferes with thefrequency range of the dwell, the dwell may be delayed in any suitableway, for example, by being placed in the delay queue.

As discussed above in connection with FIGS. 2A and 2B, some embodimentsof the invention may be implemented using system 208 including FPGA 210and OFP 212. However, the invention is not limited in this respect, asany suitable implementation may be used. FIG. 6 is a programming logicdiagram illustrating an example implementation of FPGA 210. However, thelogic illustrated in FIG. 6 need not be implemented as an FPGA, as anysuitable implementation may be used. For example, system 600 may beimplemented in software, hardware, or any suitable combination thereof.OFP 212, which may also be included in system 208, may control operationFPGA 210.

System 600 may receive an Advance Slot Notification (ASN) input 602. Insome embodiments where the data link is a TDMA data link, the data linkmay provide the ASN signal at or near a slot boundary. For example, ASNinput 602 is located in time relative to data link slots. ASN input 602and the data link may be synchronized such that transition of the ASNsignals occurs within ±2 μs of an actual slot boundary. In someembodiments, data link slots may be 7.8125 ms in duration, however, theinvention is not limited in this respect, as any suitable slot durationmay be used. Another input provided to system 600 is an input 604, whichmay be a collection of signals provided to registers 608, 610, 612, 614,616, and 618, as described below in greater detail.

A transition detector 622 may detect when an ASN transition occurs,i.e., when the ASN signal transitions from a low state to a high stateor vice versa. An intra-slot counter 624 tracks slot boundaries. Forexample, intra-slot counter 624 may be incremented at a predeterminedfrequency and contains a number of bits (e.g., 19) sufficient torepresent a sum of ΔT and SW, wherein ΔT is a time increment and SW is aslot width represented in time units. The SW may be set by a register610 which may be, for example, a 19-bit register. The ΔT may be set by aregister 608 which may be, for example, an 8-bit register, andcorresponds to a deviation of the ASN transitions relative to the actualslot boundary. In one embodiment of the invention, ΔT may vary from 2 μsto 10.2 μs. It should be appreciated however that other suitable valuesof ΔT may be used, as the invention is not limited in this respect. Bothregisters 608 and 610 may be loaded by SBC 208 or in any other suitableway.

Intra-slot counter 624 may be reset to zero by SBC 208 whenever an ASNtransition occurs. Alternatively, intra-slot counter 624 may be reset toΔT if it reaches (SW+ΔT), which may indicate that intra-slot timecounter 624 has failed to recognize a transition to a new transmit slotbecause an immediately preceding slot had the same state as the currentslot.

A slot clock 629 may pulse at the end of every ASN slot, whether the ASNslot is active (i.e., a transmit slot) or not. The period of slot clock619 may be the SW and may be generated when an intra-slot time (recordedby intra-slot counter 624) equals SW-ΔT. Thus, the slot clock pulses oneach slot boundary.

System 600 may provide a slot number counter 632 which may be reset tozero upon initialization or when it becomes equal to its predeterminednumber of states (block 634). In one embodiment, the number of statesmay be 98,304. A total slot counter 630 coupled to slot clock 629 andslot number counter 632 may also be provided and may be reset to zeroupon initialization or at any other suitable time, such as, for example,when instructed by SBC 208. Total slot counter 630 may be incremented byslot clock 629.

A delayed ASN shift register 640 may provide a notification M slots inadvance whether a slot is a transmit slot. M may be any suitable number,such as, for example, eight. ASN shift register 640 may generate 32delayed ASN slots, with ASN slot 31 having zero delay and ASN slot 00having 31-slots delay. Transitions of the delayed ASN slots may bealigned with those of ASN input 602 to within ±ΔT. A delayed ASN output643 may be generated by clocking ASN input 602 into delayed ASN shiftregister 640 clocked by slot clock 629. A multiplexer 642 may takeinputs (32, in some embodiments of the invention) of delayed ASN shiftregister 640 and select one that corresponds to the current time. Thestate of multiplexer 624 at its output may indicate whether the datalink will transmit during the current time.

Delayed ASN output 643 may provide the ASN delayed M slots to real-time,where M may be provided by a register 618 loaded by SBC 208. In someembodiments, M may be equal to eight, i.e., delayed ASN output 643 mayindicate eight slots in advance whether a slot will be a transmit slot.However, the invention is not limited in this respect, as any othersuitable number of slots may be used.

In some situations, such as, for example, when the delay queue is fullor if a dwell has been in the delay queue for duration of time equal toa predetermined limit on the amount of time the dwell can spend in thequeue, the data link transmission may be suppressed. Accordingly, system600 may provide a data link suppress transmission signal 645. Forexample, a value of the data link suppress transmission signal 645 maybe set high if the data link transmission is to be suppressed and lowotherwise, or set in any other suitable way. To produce signal 645,register 618 may receive a suppress transmit signal that may be set highif the data link transmission is to be suppressed and low otherwise. Anoutput of register 618 may be provided to a multiplexer 620. A logicalAND gate 644 may then combine an output of multiplexer 620 with thedelayed ASN output 643 to provide data link suppress transmission signal645. Gate 644 may provide data link suppress transmission discrete 645only if a slot to be suppressed is active. Therefore, only ifmultiplexer 642 provides an output indicative of an active slot, maygate 644 produce data link suppress transmission signal 645.

System 600 may include a suppressed transmit slot counter 654 that maybe reset to zero upon initialization or in any other suitable way, suchas, for example, when instructed by SBC 208. Suppressed transmit slotcounter 654 may be incremented by a logical AND of data link suppresstransmission signal 645 and an inverted slot clock 629 (e.g., using aninverter 650), using an AND gate 652, in such a way that it isincremented if any part of a slot is suppressed. Thus, suppressedtransmit slot counter 654 may be incremented each time a slot issuppressed.

If an analysis dwell (e.g., a PMA dwell, an STD dwell, or an SMA dwell)is executed, suppressed transmit slot counter 654 and total slot counter630 may be used to compute a data link suppression duty cycle, which isperformed by dividing a value of suppressed transmit slot counter 654 bya value of total slot counter 630 and multiplying the result by 100. Athus obtained value may be rounded to a nearest integer. The data linksuppression duty cycle indicates a percent of time that the data linksuppress transmission is active and may be used to determine whether aperformance of the data link is being adversely affected. This providesan indication of how efficiently the data link operates, given that itstransmission may be suppressed.

In some embodiments, system 600 may include BIT registers (e.g., BIT ASNshift register 614 and BIT suppress shift register 616), which may beused to simulate functionality provided by system 600 during itsoperation (e.g., may provide a BIT mode). BIT suppress register 616 maybe used to simulate suppression of a data link transmission when aserial output of BIT suppress shift register 616 is connected in placeof the suppress transmit input of register 618 (e.g., using multiplexer610). BIT ASN shift register 614 may provide the BIT mode when a serialoutput of BIT ASN shift register 614 is connected in place of the ASNinput 606 (e.g., using a multiplexer 606). During the BIT mode, BITshift registers 614 and 616 may shift circularly when intra-slot counter624 equals to slot width SW. In some embodiments, BIT shift registers614 and 616 do not shift when the BIT mode is not active.

In addition to suppressed transmit slot counter 654, system 600 mayinclude a suppress time counter 660 which may be reset to zero uponinitialization or in any other suitable way, such as, for example, wheninstructed by system 208. A multiplexer 662 may receive, at its firstinput, an output of register 618 and, at its second input, data linksuppress transmission signal 645, and output a multiplexed signal whichmay then be provided to suppress time counter 660. A first output 664 ofmultiplexer 660 may be provided to the data link to suppresstransmission. A second output of multiplexer 660 may be provided tosuppress time counter 660 that may be incremented when a selected inputof multiplexer 660 receives high value. System 600 may provide a totaltime counter 636 that may be reset to zero upon initialization or in anyother suitable way, such as, for example, when instructed by system 208.Similarly to suppressed transmit slot counter 654, suppress time counter660, together with total time counter 636, may be used to compute thedata link suppression duty cycle. To compute the data link suppressionduty cycle, a value of suppress time counter 660 may be divided by avalue of total time counter 636, a result of which may be multiplied by100. A thus obtained value may be rounded to a nearest integer. The datalink suppression duty cycle may indicate a percent of time that the datalink suppress transmission is active and may be used to determinewhether a performance of the data link is being adversely affected. Theduty cycle may be utilized to configure parameters used by system 600.For example, if the duty cycle is high, the predetermined size of thedelay queue and/or the predetermined amount of time a dwell can spend inthe delay queue may be decreased to allow for more frequent execution ofdwells. If the duty cycle is low, the predetermined size of the delayqueue and/or the predetermined amount of time a dwell can spend in thedelay queue may be increased, because the data link transmits a smallportion of its operating time.

In addition to the counters described above, system 600 may include atransmit slot counter 638 which may be driven by a logical AND gate 648.First and second inputs of gate 648 may be the output of multiplexer 642and slot clock signal 629, respectively. Transmit slot counter 638 maykeep track of a number of past slots that were transmit slots.

During data link operation, an interrupt in the signal transmission maybe desired to perform some additional processing. Accordingly, a certainnumber of slots may be masked off, so that the data link does nottransmit during these slots, to produce the interrupt in data linktransmission. To implement the interrupt, an N slot gap detector 646 maybe used to generate an N-slot gap interrupt when a gap (i.e., a numberof consecutive slots that are not transmit slots) of N slots or greateris detected. For example, N may range from 0 to 32. A value of zeromeans that no interrupt is to be generated, and values of 1 to 32represent gap widths of 1 to 32 slots. The interrupt may occur early inthe first slot of the gap, at an intra-slot time of ΔT. Register 612 maysupply N, the number of consecutive inactive slots, to N slot gapdetector 646. It should be noted that, in some embodiments, N may not begreater than M+1, where M is the number of slots in advance of which theASN signal transitions, as described above.

When the interrupt is generated, a current value of slot number counter632 may be stored in an interrupt slot number register 656. Thisinformation may be used to time dwells that may occur during gaps in thedata link transmission. A value of interrupt slot number register 656may be updated upon interrupt whether masked or not. A mask 666 mayreceive a signal to mask off ASN transmit slots and may provide a signalto an interrupt block 668.

When the N-slot gap warning interrupt is generated, system 600 maydetermine the width of the gap, which may be stored in aslots-to-end-of-gaps register 658. When the interrupt first occurs, thisvalue will be N, but it increases if additional sequential non-transmitslots occur. A value of slots-to-end-of-gaps register 658 may be updatedupon interrupt whether masked or not.

Having thus described several aspects of at least one embodiment of thisinvention, it is to be appreciated that various alterations,modifications, and improvements will readily occur to those skilled inthe art.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andscope of the invention. Accordingly, the foregoing description anddrawings are by way of example only.

The above-described embodiments of the present invention can beimplemented in any of numerous ways. For example, the embodiments may beimplemented using hardware, software or a combination thereof. Whenimplemented in software, the software code can be executed on anysuitable processor or collection of processors, whether provided in asingle computer or distributed among multiple computers.

Further, it should be appreciated that a computer may be embodied in anyof a number of forms, such as a rack-mounted computer, a desktopcomputer, a laptop computer, or a tablet computer. Additionally, acomputer may be embedded in a device not generally regarded as acomputer but with suitable processing capabilities, including a PersonalDigital Assistant (PDA), a smart phone or any other suitable portable orfixed electronic device.

Also, a computer may have one or more input and output devices. Thesedevices can be used, among other things, to present a user interface.Examples of output devices that can be used to provide a user interfaceinclude printers or display screens for visual presentation of outputand speakers or other sound generating devices for audible presentationof output. Examples of input devices that can be used for a userinterface include keyboards, and pointing devices, such as mice, touchpads, and digitizing tablets. As another example, a computer may receiveinput information through speech recognition or in other audible format.

Such computers may be interconnected by one or more networks in anysuitable form, including as a local area network or a wide area network,such as an enterprise network or the Internet. Such networks may bebased on any suitable technology and may operate according to anysuitable protocol and may include wireless networks, wired networks orfiber optic networks.

Also, the various methods or processes outlined herein may be coded assoftware that is executable on one or more processors that employ anyone of a variety of operating systems or platforms. Additionally, suchsoftware may be written using any of a number of suitable programminglanguages and/or conventional programming or scripting tools, and alsomay be compiled as executable machine language code or intermediate codethat is executed on a framework or virtual machine.

In this respect, the invention may be embodied as a computer readablemedium (or multiple computer readable media) (e.g., a computer memory,one or more floppy discs, compact discs, optical discs, magnetic tapes,flash memories, circuit configurations in Field Programmable Gate Arraysor other semiconductor devices, etc.) encoded with one or more programsthat, when executed on one or more computers or other processors,perform methods that implement the various embodiments of the inventiondiscussed above. The computer readable medium or media can betransportable, such that the program or programs stored thereon can beloaded onto one or more different computers or other processors toimplement various aspects of the present invention as discussed above.

The terms “program” or “software” are used herein in a generic sense torefer to any type of computer code or set of computer-executableinstructions that can be employed to program a computer or otherprocessor to implement various aspects of the present invention asdiscussed above. Additionally, it should be appreciated that accordingto one aspect of this embodiment, one or more computer programs thatwhen executed perform methods of the present invention need not resideon a single computer or processor, but may be distributed in a modularfashion amongst a number of different computers or processors toimplement various aspects of the present invention.

Computer-executable instructions may be in many forms, such as programmodules, executed by one or more computers or other devices. Generally,program modules include routines, programs, objects, components, datastructures, etc. that perform particular tasks or implement particularabstract data types. Typically the functionality of the program modulesmay be combined or distributed as desired in various embodiments.

Various aspects of the present invention may be used alone, incombination, or in a variety of arrangements not specifically discussedin the embodiments described in the foregoing and is therefore notlimited in its application to the details and arrangement of componentsset forth in the foregoing description or illustrated in the drawings.For example, aspects described in one embodiment may be combined in anymanner with aspects described in other embodiments.

Use of ordinal terms such as “first,” “second,” “third,” etc., in theclaims to modify a claim element does not by itself connote anypriority, precedence, or order of one claim element over another or thetemporal order in which acts of a method are performed, but are usedmerely as labels to distinguish one claim element having a certain namefrom another element having a same name (but for use of the ordinalterm) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose ofdescription and should not be regarded as limiting. The use of“including,” “comprising,” or “having,” “containing,” “involving,” andvariations thereof herein, is meant to encompass the items listedthereafter and equivalents thereof as well as additional items.

1. A method for coordinating detection of emitted signals withtransmission of signals in a platform having at least one transmitterthat transmits signals in a first frequency range and at least onereceiver system adapted to perform a previously computed scan strategycomprising a set of a plurality of dwells, the method comprising actsof: modifying the previously computed scan strategy during performance,by the at least one receiver system, of at least a portion of thepreviously computed scan strategy by: determining a first time at whichat least one signal in the first frequency range is scheduled fortransmission by the at least one transmitter; identifying, in thepreviously computed scan strategy, a first dwell from the plurality ofdwells that is scheduled to be executed during the first time;determining whether a frequency range of the first dwell of thepreviously computed scan strategy conflicts with the first frequencyrange; and in response to determining that the frequency range of thefirst dwell of the previously computed scan strategy conflicts with thefirst frequency range, delaying execution of the first dwell forexecution at a later time, wherein the act of delaying execution of thefirst dwell further comprises placing the first dwell in a delay queue.2. The method of claim 1, wherein the delay queue imposes a limit on anamount of time that the first dwell can remain in the delay queue. 3.The method of claim 1, wherein the method further comprises acts of:determining that the delay queue is full; and in response to determiningthat the delay queue is full, selecting a dwell in the delay queue forexecution based on an amount of time the dwell has been in the delayqueue.
 4. The method of claim 1, wherein the act of determining thefirst time at which the at least one signal in the first frequency rangeis scheduled for transmission further comprises receiving a notificationfrom the transmitter indicating a time at which the transmitter isscheduled to transmit.
 5. The method of claim 4, wherein thenotification is received in advance of the scheduled transmission. 6.The method of claim 1, wherein the transmitter communicates according toa time division multiple access (TDMA) protocol.
 7. At least onecomputer storage device that stores instructions that, when executed,perform a method for coordinating detection of emitted signals withtransmission of signals in a platform having at least one transmitterthat transmits signals in a first frequency range and at least onereceiver system adapted to perform a previously computed scan strategycomprising a set of a plurality of dwells, the method comprising actsof: modifying the previously computed scan strategy during performance,by the at least one receiver system, of at least a portion of thepreviously computed scan strategy by: determining a first time at whichat least one signal in the first frequency range is scheduled fortransmission by the at least one transmitter; identifying, in thepreviously computed scan strategy, a first dwell from the plurality ofdwells that is scheduled to be executed during the first time;determining whether a frequency range of the first dwell of thepreviously computed scan strategy conflicts with the first frequencyrange; and in response to determining that the frequency range of thefirst dwell of the previously computed scan strategy conflicts with thefirst frequency range, delaying execution of the first dwell forexecution at a later time, wherein the act of delaying execution of thefirst dwell further comprises placing the first dwell in a delay queue.8. The at least one computer storage device of claim 7, wherein thedelay queue imposes a limit on an amount of time that the first dwellcan remain in the delay queue.
 9. The at least one computer storagedevice of claim 7, wherein the method further comprises acts of:determining that the delay queue is full; and in response to determiningthat the delay queue is full, selecting a dwell in the delay queue forexecution based on an amount of time the dwell has been in the delayqueue.
 10. The at least one computer storage device of claim 7, whereinthe act of determining the first time at which the at least one signalin the first frequency range is scheduled for transmission furthercomprises receiving a notification from the transmitter indicating atime at which the transmitter is scheduled to transmit.
 11. The at leastone computer storage device of claim 10, wherein the notification isreceived in advance of the scheduled transmission.
 12. The at least onecomputer storage device of claim 7, wherein the transmitter communicatesaccording to a time division multiple access (TDMA) protocol.
 13. Atleast one receiver system adapted to perform previously computed scanstrategy comprising a set of a plurality of dwells and configurable tooperate with at least one transmitter that transmits signals in a firstfrequency range, the at least one receiver system comprising: at leastone controller that modifies the previously computed scan strategyduring performance, by the at least one receiver system, of at least aportion of the previously computed scan strategy by: determining a firsttime at which at least one signal in the first frequency range isscheduled for transmission by the at least one transmitter; identifying,in the previously computed scan strategy, a first dwell from theplurality of dwells that is scheduled to be executed during the firsttime; determining whether a frequency range of the first dwell of thepreviously computed scan strategy conflicts with the first frequencyrange; and in response to determining that the frequency range of thefirst dwell of the previously computed scan strategy conflicts with thefirst frequency range, delaying execution of the first dwell forexecution at a later time, wherein the at least one controller placesthe first dwell in a delay queue in response to determining that thefrequency range of the first dwell conflicts with the first frequencyrange.
 14. The at least one receiver system of claim 13, wherein thedelay queue imposes a limit on an amount of time that the first dwellcan remain in the deley queue.
 15. The at least one receiver system ofclaim 13, wherein the at least one controller: determines that the delayqueue is full; and in response to determining that the delay queue isfull, selects a dwell in the delay queue for execution based on anamount of time the dwell has been in the delay queue.
 16. The at leastone receiver system of claim 12, wherein the at least one controller:receives a notification from the transmitter indicating a time at whichthe transmitter is scheduled to transmit.
 17. The at least one receiversystem of claim 16, wherein the notification is received in advance ofthe scheduled transmission.
 18. A method for coordinating detection ofemitted signals with transmission of signals in a platform having atleast one transmitter that transmits signals in a first frequency rangeand at least one receiver system adapted to perform a previouslycomputed scan strategy comprising a plurality of dwells, the methodcomprising acts of: modifying the previously computed scan strategyduring performance, by the at least one receiver system, of at least aportion of the previously computed scan strategy by: determining a firsttime at which at least one signal in the first frequency range isscheduled for transmission by the at least one transmitter; selecting,in the previously computed scan strategy, a first dwell from theplurality of dwells to be executed at the first time; determiningwhether a frequency range of the first dwell of the previously computedscan strategy conflicts with the first frequency range; when it isdetermined that the frequency range of the first dwell of the previouslycomputed scan strategy conflicts with the first frequency range,delaying execution of the first dwell, wherein the act of delayingexecution of the first dwell further comprises placing the first dwellin a delay queue; determining that the delay queue is full; and inresponse to determining that the delay queue is full, selecting a dwellin the delay queue for execution based on an amount of time the dwellhas been in the delay queue.